1. Field
The present invention pertains to a phase detection apparatus and a phase synchronization apparatus applicable to transmission apparatuses using a high-speed clock and clock generators.
2. Description of the Related Art
Conventional phase synchronization apparatuses that detect and synchronize phases include a phase lock loop frequency synthesizer. Phase synchronization apparatuses are applied to transmission apparatuses for example and generate a given frequency. FIG. 14 is a circuit diagram of a conventional transmission apparatus. A transmission apparatus 1000 depicted in FIG. 14 has a configuration of a transmission circuit of an optical transmission apparatus using optical fibers. A signal from a serializer/deserializer (SERDES) 1001 is transmitted as an optical signal from a light receiving element 1003 such as a laser diode (LD) driven by a driver (DRV) 1002. The SERDES 1001 includes a multiplexer (MUX) 1004 and a flip flop (FF) 1005. The SERDES 1001 is connected to a clock multiplication unit (CMU) 1010 and a 1/n-frequency divider (frequency divider) 1011.
The CMU 1010 is widely used in, for example, transmission circuits and clock generators of transmission apparatuses and outputs a clock signal Ck(f) to the FF 1005 of the SERDES 1001 and the frequency divider 1011. The frequency divider 1011A outputs a clock signal Ck(f/n) to the CMU 1010 as feedback and further outputs the clock signal Ck(f/n) to the MUX 1004 of the SERDES 1001.
The symbol “f” denotes a frequency of a high-speed clock and “n” is an integer. A symbol “fr” denotes a reference clock supplied from an external source (a crystal oscillator or a stable system-clock). The CMU 1010 is used to synchronize the reference clock fr with the output of the transmission apparatus. The symbol Ck(f/n) is a clock signal (Ck(f/n)=fp) whose frequency f is divided by n. A frequency of the clock signal Ck(f) output from the CMU 1010 is a high-frequency clock with a rate n times fr, thereby enabling faster data transmission rates.
FIG. 15 is a circuit diagram of an internal structure of the CMU depicted in FIG. 14. The CMU 1010 includes a phase detector (PD) 1101, a charge pump (CP) 1102, a low pass filter (LPF) 1103, and a voltage control oscillator (VCO) 1104.
The PD 1101 is an important constituent of the CMU 1010 and the characteristics of the PD 1101 influence the accuracy and quality of a clock signal. Accuracy requires phase errors to be minimized while quality requires jitter and noise to be minimized. The operating frequency of a multiplexer (MUX) employing the CMU 1010 has improved, reaching 10 GHz, 20 GHz, 30 GHz, and above.
Output signals up and dn output from the PD 1101 are input to the CP 1102. The CP 1102 outputs a voltage V_CP, and the LPF 1103 outputs a voltage V_LPF. For example, when Ck(f/n) is faster than fr, the PD 1101 generates and outputs the output signal dn (continual pulse signal) to the CP 1102. The voltage V_CP output from the CP 1102 and the voltage V_LPF output from the LPF 1103 gradually change together until V_LPF reaches a constant voltage (value).
It is known that the maximum usable (operating) frequency of an element such as a logic gate used in the PD 1101 is limited. Particularly, when CMOS and BiCMOS are used, higher operating frequencies (for example, a transmission apparatus with 40 Gbps) for faster data transmission have not yet been achieved. Conventionally, the PD 1101 does not operate fast enough, one reason of which is a dead zone of the PD 1101.
FIG. 16 is a circuit diagram depicting an example of a conventional phase detecting unit. The PD 1101 depicted in FIG. 16 uses two delay elements 1, 2 (1201, 1202) that induce a given delay. The dead zone is invoked by an “insensitive” area of logic gates 1 and 2 (1211, 1212) that detect a difference between clocks fr and fp. The clocks fr and fp are input signals that are phase-delayed by and output from the delay elements 1 and 2 (1201, 1202) as signals fr2 and fp2. In this way, the logic gates 1 and 2 (1211, 1212) operate preventing the dead zone.
Japanese Patent Application Laid-Open Publication No. H9-223960 discloses that a PD includes multiple delay elements, multiple phase comparators, and an adder to prevent the dead zone.
The dead zone of the PD 1101 is defined as a state in which the PD 1101 cannot distinguish phase differences between the clocks fr and fp. The dead zone does not change the signals up and dn output from the PD 1101 even if there is a change in phase between the clocks fr and Ck(f/n). The CMU 1010 continues to operate with a certain operating frequency even if the clock Ck(f/n) is not equal to the frequency of the clock fr. The VCO 1104 outputs a certain natural frequency (free running frequency) even without any input. In this case, a frequency error (frequency mismatch) occurs in the frequencies of the clocks Ck(f) and Ck(f/n), thereby causing a phase error of clock signals. Such phase errors gradually accumulate until the PD 1101 can detect the phase difference between the clocks fr and Ck(f/n). When the output signal up or dn appears again, ripples (fluctuation) occur in V_LPF.
Even if the dead zone is eliminated using a pair of delay elements, there is still a problem of mismatch of transistors or switches. When a bipolar transistor is used for the CP 1102 of FIG. 16, a mismatch occurs due to the differing properties of a pair of transistors: the p-n-p transistor 1221 and the n-p-n transistor 1222. The p-n-p transistor 1221 and the n-p-n transistor 1222 do not have identical properties. As a constant current source, a pair of transistors 1231 and 1232 is used. When a CMOS is used for the CP 1102, a mismatch occurs due to the differing properties of the paired nMOSFET and PMOSFET.
FIG. 17 is a timing chart depicting operation of a conventional phase-detecting unit. The output signals up and dn depicted in FIG. 16 are output during any of the following states:    (1) a period in which the clock fr is earlier than the clock fp (early);    (2) a period in which the clock fr is slightly earlier than the clock fp (Lock+error);    (3) a period in which the clock fr and the clock fp are in a synchronized (locked) state (Lock).
The relative timing of signals is similar when the clock fr is later than the clock fp; hence, for brevity explanation is omitted herein.
As FIG. 17 depicts, conventionally the PD 1101 continuously outputs, regardless of the period, the output signals up and dn, the output signals up and dn overlapping each other. Consequently, ripples occur in the voltage (V_LPF) output from the LPF 1103 during the period of the locked state (3) due to the mismatch of transistors. It is difficult to remove the ripples completely, limiting a gain bandwidth of the LPF 1103. The ripples eventually appear in the clock Ck(f) output from the VCO 1104 as jitter (see FIG. 15). Jitter lowers communication quality (for example, bit error rate (BER)) of a MUX or a transmission apparatus, or limits the maximum operating frequency of the CMU 1010.
The conventional PD 1102 cannot resolve the problem of propagation delay of the logic gates 1 and 2 (1211, 1212), thereby limiting the frequency of the input clocks fr and fp, and limiting the operating frequency to a relatively low value.